1. Field of the Invention
The present invention relates to a variable delay circuit and a phase adjustment circuit using the variable delay circuit.
2. Description of the Related Art
Data input and output is performed in synchronization with a clock signal in order to realize high speed data transfer. Especially when the frequency of the clock signal exceeds 100 MHz, an external cloak supplied from outside a semiconductor integrated circuit and an internal clock used inside the semiconductor integrated circuit need to be synchronized with each other using a PLL (Phase Locked Loop) or a DLL (Delay Locked Loop).
Digital PLL and DLL using a digital delay circuit has an advantage of being designed more easily than analog PLL and DLL, but has a disadvantage that the resolution of the phase cannot be smaller than the delay amount of one gate of the digital delay circuit.
As one solution of such a disadvantage, Japanese Laid-Open Publication No. 10-276074 discloses a method for realizing a smaller resolution time period than the delay amount of one gate of a digital delay circuit. According to this method, a resolution time period xcex1 is realized by combining a delay gate having a delay amount of td and a delay gate having a delay amount of td+xcex1.
For example, delay having a delay time period in the range of 10td to 11td and a resolution time period of 0.1td can be realized by connecting N1 pieces of delay gates each having a delay amount of td and N2 pieces of delay gates each having a delay amount of 1.1td in series under the condition of, for example, N1+N2=10. For example, when N1=7 and N2=3, a delay time period of 10.3td can be realized.
However, according to the method described in the above-mentioned publication, as the range of the delay time period which can be set enlarges, the lower limit of the range of the delay time period which can be set rises undesirably.
For example, in order to realize a delay having a resolution time period of 0.1td and a range of delay time period which can be set of 2td, it is necessary to connect N1 pieces of delay gates each having a delay amount of td and N2 pieces of delay gates each having a delay amount of 1.1td in series under the condition of N1+N2=20. In such a case, the lower limit of the range of delay time period which can be set is as high as 20td.
The method described in the above-mentioned publication has another disadvantage in that as the resolution time period becomes more precise, the lower limit of the range of delay time period which can be set rises.
For example, in order to realize a delay having a resolution time period of 0.05td, it is necessary to connect N, pieces of delay gates each having a delay amount of td and N2 pieces of delay gates each having a delay amount of 1.05td in series under the condition of N1+N2=20. In such a case, the lower limit of the range of delay time period which can be set is as high as 20td.
According to one aspect of the invention, a variable delay circuit includes a plurality of delay circuits for delaying an input signal; and a selection circuit for selecting an output from one of the plurality of delay circuits in accordance with a selection signal. The plurality of delay circuits include a first delay circuit for delaying the input signal by a first delay time period and a second delay circuit for delaying the input signal by a second delay time period which is longer than the first delay time period. The difference between the first delay time period and the second delay time period is shorter than a minimum delay time period which is allowed to be set in the first delay circuit.
According to another aspect of the invention, a phase adjustment circuit includes a first variable delay circuit for delaying an input signal; a second variable delay circuit for controlling a delay time period at a higher precision than the first variable delay circuit; and a control circuit for variably controlling a delay time period of the first variable delay circuit and a delay time period of the second variable delay circuit. An output from the first variable delay circuit is delayed by the second variable delay circuit to provide an output signal having a prescribed phase relationship with respect to the input signal. The second variable delay circuit includes a plurality of delay circuits for delaying the output from the first variable delay circuit, and a selection circuit for selecting an output from one of the plurality of delay circuits in accordance with a selection signal. The plurality of delay circuits include a first delay circuit for delaying the output from the first variable delay circuit by a first delay time period and a second delay circuit for delaying the output from the first variable delay circuit by a second delay time period which is longer than the first delay time period. The difference between the first delay time period and the second delay time period is shorter than a minimum delay time period which is allowed to be set in the first delay circuit.
In one embodiment of the invention, a range of delay time period which is allowed to be set in the second variable delay circuit is greater than a resolution time period of the first variable delay circuit.
In another embodiment of the invention, a target delay time period exceeds a range of the delay time period which is allowed to be set in the second variable delay circuit, the control circuit resets the delay time period of the first variable delay circuit and resets the delay time period of the second variable delay circuit at substantially a center of the range of the delay time period which is allowed to be set in the second variable delay circuit.
According to a variable delay circuit of the present invention, an output from one of a plurality of delay circuits for delaying an input signal is selected by a selection circuit, and the selected output is provided as an output signal. The plurality of delay circuit include a first delay circuit for delaying the input signal by a first delay time period and a second delay circuit for delaying the input signal by a second delay time period which is longer than the first delay time period. The difference between the first delay time period and the second delay time period is shorter than a minimum delay time period which can be set in the first delay circuit. Thus, the range of the delay time period which can be set in the variable delay circuit it not limited to any prescribed range and can be as large as required. The lower limit of the delay time period which can be set in the variable delay circuit is fixed regardless of the range of the delay time period which can be set in the variable delay circuit.
Furthermore, a phase adjustment circuit including the above-described variable delay circuit as a second variable delay circuit is provided. Such a phase adjustment circuit outputs a signal having a prescribed phase relationship with respect to the input signal.
A range of the delay time period, which can be set in the second variable delay circuit, can be greater than a resolution time period of the first variable delay circuit. Thus, the possibility of adjusting the phase of the input signal is increased by adjusting the delay time period of the second variable delay circuit without resetting the delay time period of the first variable delay circuit. As a result, the number of times that the delay time period of the first variable delay circuit is reset can be reduced.
When the delay time period of the second variable delay circuit is reset, the delay time period of the second variable delay circuit is reset to substantially a center of the range of delay time period which can be set in the second variable delay circuit. Thus, the phase relationship between the input signal and the output signal can be adjusted at a high speed.
Thus, the invention described herein makes possible the advantages of providing a variable delay circuit for maintaining the lower limit of the range of the delay time period which can be set regardless of the range of the delay time period or the precision of the resolution time period, and a phase adjustment circuit using the variable delay circuit.
These and other advantages of the present invention will become apparent to those skilled in the art upon reading and understanding the following detailed description with reference to the accompanying figures.